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Both the load and store instruction types need to access the data memory Hence a pipeline stage must be devoted to this subcomputation The fifth stage of the pipeline, labeled MEM, is included for this purpose Both the ALU and load instruction types must write a result back to the register file as their last subcomputation An ALU instruction writes the result of the operation performed on the register operands into a destination register A load instruction loads into the destination register the data fetched from memory No memory access is required by an ALU instruction; hence, the writing back to the destination register can theoretically take place immediately after the ALU stage However, for the purpose of unifying with the register write-back subcomputation of the load instruction type, the register write-back subcomputation for ALU instructions is delayed by one pipeline stage and takes place in the sixth pipeline stage, named WB This incurs one idle machine cycle for ALU instructions in the MEM pipeline stage This is a form of external fragmentation and introduces some inefficiency in the pipeline For conditional branch instructions, the branch condition must be determined prior to updating the program counter Since the ALU functional unit is used to perform effective address generation, it cannot be used to perform the branch condition evaluation If the branch condition evaluation involves only the checking of a register to determine if it is equal to zero, or if it is positive or negative, then only a simple comparator is needed This comparator can be added, and the earliest pipeline stage in which it can be added is the ALU stage, that is, after the reference register is read in the RD stage Hence, the earliest pipeline stage in which the program counter can be updated with the branch target address, assuming the conditional branch is taken, is during the MEM stage, that is, after the target address is computed and the branch condition is determined in the ALU stage The foregoing coalescing of resource requirements for the different instruction types resulted in the six-stage instruction pipeline shown in the right-hand side of Figure 210 This instruction pipeline is identified as the TYPICAL (TYP) instruction pipeline and is used in the remainder of this chapter as an illustration vehicle Other than the one idling pipeline stage (MEM) for ALU instructions, store and branch instruction types also incur some external fragmentation Both store and branch instructions do not need to write back to a register and are idling during the WB stage Overall this six-stage instruction pipeline is quite efficient Load instructions use all six stages of the pipeline: the other three instruction types use five of the six stages In unifying different instruction types into one instruction pipeline, there are three optimization objectives- The first is to minimize the total resources required to support all the instruction types In a way, the objective is to determine the pipeline that is analogous to the least common multiple of all the different resource requirements The second objective is to maximize the utilization of all the pipeline stages by the different instruction types, in other words, to minimize the idling stages incurred by each instruction type Idling stages lead to external fragmentation and result in inefficiency and throughput penalty The third objective is to minimize the overall latency for each of the instruction types Hence, if an idling stage is unavoidable for a particular instruction type and there is flexibility in terms of the placement of that idling stage, then it is always better to place it at the end of the pipeline This. pdf to word c# c# code for convert . pdf file to . docx - CodeProject
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